High precision capacitors are often needed in integrated circuits. For example, some of the capacitor requirements in a true eighteen bit analog-to digital or digital-to-analog converter are a ratio stability of less than 0.00075% over 10 years, a voltage coefficient of less than 10 ppm per volt, a temperature drift match of less than 0.05% per ° C., a dielectric absorption of less than 0.00075%, and a capacitance of greater than 0.5 femtofarads per square micrometer.
Such integrated circuit capacitors are generally formed as part of a fabrication process whereby a thin dielectric layer is established between two metallic plates. For example, a thin dielectric layer may be established between a bottom plate formed from silicided polysilicon gate material and a top plate of a deposited metal, or a thin dielectric layer may be established between a bottom plate of interconnect material and a top plate of a deposited metal. A crucial step in manufacturing high precision integrated circuit capacitors is the formation of the capacitor plates. In manufacturing the capacitors, the capacitor plates are typically formed by etching one or more conductive layers to a desired shape. Current etch techniques may limit the precision of the capacitors so formed by producing nonlinear etch profiles, by leaving filaments of the material being etched, by trenching the surface of underlying layers, and by damaging the capacitor dielectric along the edges of the capacitor. There is therefore a need for a method to form high precision integrated circuit capacitors that is not limited by conventional etching constraints.